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參數(shù)資料
| 型號(hào)： | HYMR1616-845 |
| 英文描述： | RAMBUS DRAM Module |
| 中文描述： | Rambus的內(nèi)存 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 111K |
| 代理商： | HYMR1616-845 |
Page 8
Rev. 0.0/ Feb. 99
Preliminary
HYMR11648/11848 Series
Timing Parameters
The following timing parameters are from the RDRAMs
pins, not the RIMM. Please refer to the RDRAM datasheet
for detailed timing diagrams.
Parameter
Description
Min
-40
-800
Min
-45
-800
Min
-53
-600
Max
Units
t
RC
Row Cycle time of RDRAM banks -the interval between ROWA packets
with ACT commands to the same bank.
28
28
28
-
t
CYCLE
t
RAS
RAS-asserted time of RDRAM bank - the interval between ROWA
packet with ACT command and next ROWR packet with PRER
a
com-
mand to the same bank.
20
20
20
60
μ
s
b
t
CYCLE
t
RP
Row Precharge time of RDRAM banks - the interval between ROWR
packet with PRER
a
command and next ROWA packet with ACT com-
mand to the same bank.
8
8
8
-
t
CYCLE
t
PP
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRER
a
commands to any banks of the
same device.
8
8
8
-
t
CYCLE
t
RR
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
8
8
8
-
t
CYCLE
t
RCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT com-
mand to COLC packet with RD or WR command). Note - the RAS-to-
CAS delay seen by the RDRAM core (t
RCD,CORE
) is equal to t
RCD,CORE
= 1 + t
RCD
because of differences in the row and column paths through
the RDRAM interface.
7
9
7
-
t
CYCLE
t
CAC
CAS Access delay - the minimum interval from RD command to Q read
data.
8
8
8
12
t
CYCLE
t
CWD
t
CC
CAS Write Delay (interval from WR command to D write data.
6
6
6
6
t
CYCLE
t
CYCLE
CAS-to-CAS time of RDRAM bank - the interval between successive
COLC commands).
4
4
4
-
t
PACKET
t
RTR
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
t
CYCLE
t
CYCLE
Interval from COLC packet with WR command to COLC packet which
causes retire, and to COLM packet with bytemask.
8
8
8
-
t
OFFP
The interval (offset) from COLC packet with RDA command, or from
COLC packet with retire command (after WRA automatic precharge), or
from COLX packet with PREX command to the equivalent ROWR
packet with PRER.
4
4
4
4
t
CYCLE
t
RDP
Interval from last COLC packet with RD command to ROWR packet
with PRER.
4
4
4
-
t
CYCLE
t
RTP
Interval from last COLC packet with automatic retire command to
ROWR packet with PRER.
4
4
4
-
t
CYCLE
a. Or equivalent PREC or PREX command.
b. This is a constraint imposed by the core, and is therefore in units of
μ
s rather than t
CYCLE
.
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