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參數(shù)資料
| 型號(hào)： | HYMR1832-653 |
| 英文描述： | RAMBUS DRAM Module |
| 中文描述： | Rambus的內(nèi)存 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 111K |
| 代理商： | HYMR1832-653 |
Rev. 0.0/ Feb. 99
Page 7
HYMR11648/11848 Series
Preliminary
I
DD
- V
DD
Supply Current Profile
I
CMOS
- V
CMOS
Supply Current Profile
I
DD
RIMM module power test conditions
-600
Max
-800
Max
Unit
I
DD1
All RDRAMs in powerdown, self-refresh mode
TBD/TBD
a
mA
I
DD2
All RDRAMs in NAP mode
TBD
mA
I
DD3
All RDRAMs in Standby mode, no commands
TBD
TBD
mA
I
DD4
All RDRAMs in Active mode, no commands
TBD
TBD
mA
I
DD5
All RDRAMs running refresh cycles, with t
RC
= t
RC,MIN
TBD
TBD
mA
I
DD6
All RDRAMs running refresh cycles, with t
RC
= t
REF
/# of rows
TBD
TBD
mA
I
DD7
One RDRAM cycling t
RC
= min, 1 bank, no COL packets, remainder of RDRAMs in
Standby
TBD
TBD
mA
I
DD8
One RDRAM cycling t
RC
= min, 1 bank, two dualocts per activate (32-byte transfers),
remainder of RDRAMs in Standby
TBD
TBD
mA
I
DD9
One RDRAM burst read/write, 1 bank open, full bandwidth, COL address changing every
dualoct, remainder of RDRAMs in Standby
TBD
TBD
mA
a. For modules with a -LP designator.
I
CMOS
RIMM module power test conditions
Max
Unit
I
CMOS1
Current when RDRAMs are in powerdown, self-refresh state
TBD
mA
I
CMOS2
Current when CMOS pins are used for register read/write operations (f=1MHz)
TBD
mA
I
CMOS3
Current when CMOS pins are used for power management operations (f=100MHz)
TBD
mA
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