參數(shù)資料
型號: HYR1812820G-845
廠商: INFINEON TECHNOLOGIES AG
英文描述: CONN,VERT, 5 PIN NB
中文描述: 直接的RDRAM RIMM的模塊(帶144兆RDRAMs)
文件頁數(shù): 6/14頁
文件大?。?/td> 319K
代理商: HYR1812820G-845
HYR 16xx20G/HYR 18xx20G
Rambus RIMM Modules
INFINEON Technologies
6
7.00
LDQB8
LDQB0
B32, A32, B30, A30, B28,
A28, B26, A26, B24
I/O
RSL
Data bus B. A 9-bit bus carrying a
byte of read or write data between
the Channel and the RDRAM.
LDQB8 is non-functional on
modules with x16 RDRAM devices.
LROW2
LROW0
B16, A18, B18
I
RSL
Row bus. 3-bit bus containing
control and address information for
row accesses.
LSCK
A34
I
V
CMOS
Serial Clock input. Clock source
used to read from and write to the
RDRAM control registers.
N.C.
A16, B14, A38, B38, A40,
B40, A77, B79;A43, B43,
A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48,
A49, B49, A50, B50
These pads are not connected.
These connector pads are reserved
for future use.
RCFM
B83
I
RSL
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Positive polarity.
RCFMN
B81
I
RSL
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Negative polarity.
RCMD
B59
I
V
CMOS
Serial Command Input used to read
from and write to the control
registers. Also used for power
management.
RCOL4
RCOL0
A73, B73, A71, B71, A69
I
RSL
Column bus. 5-bit bus containing
control and address information for
column accesses.
RCTM
A79
I
RSL
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Positive polarity.
RCTMN
A81
I
RSL
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Negative polarity.
RDQA8
RDQA0
A91, B91, A89, B89, A87,
B87, A85, B85, A83
I/O
RSL
Data bus A. A 9-bit bus carrying a
byte of read or write data between
the Channel and the RDRAM.
RDQA8 is non-functional on
modules with x16 RDRAM devices.
Module Connector Pad Description
(cont
d)
Signal
Module Connector Pads
I/O
Type
Description
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