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參數(shù)資料
| 型號(hào)： | HYS 72D32000GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 2.5 V 185-pin Unbuffered DDR-I SDRAM Modules(2.5 V 184腳、寄存型256M位 DDR-I SDRAM 模塊) |
| 中文描述： | 2.5伏185針緩沖的DDR - 1 SDRAM的模塊（2.5伏，寄存型256M位的DDR 184腳，我內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大小： | 164K |
| 代理商： | HYS 72D32000GU |
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HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
Preliminary Datasheet
10
5.00
Supply Voltage Levels
Parameter
Symbol
Limit Values
Unit
Notes
min.
nom.
max.
Device Supply Voltage
V
DD
V
DDQ
V
REF
V
TT
2.3
2.5
2.7
V
–
Output Supply Voltage
2.3
2.5
2.7
V
1)
Input Reference Voltage
1.15
V
REF
– 0.04
V
REF
1.25
1.35
V
REF
+ 0.04
V
2)
Termination Voltage
1)
Under all conditions,
V
DDQ
must be less than or equal to
V
DD
.
2)
Peak to peak AC noise on
V
REF
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations
in
V
DDQ
.
3)
V
TT
of the transmitting device must track
V
REF
of the receiving device.
V
3)
DC Operating Conditions (SSTL_2 Inputs)
(
V
DDQ
= 2.5 V,
T
A
= 70
°
C, Voltage Referenced to
V
SS
)
Parameter
Symbol
Limit Values
Unit
Notes
min.
V
REF
+ 0.18
– 0.30
max.
V
DDQ
+ 0.3
V
REF
– 0.18
5
DC Input Logic High
V
IH (DC)
V
IL (DC)
I
IL
I
OL
V
1)
DC Input Logic Low
V
μ
A
μ
A
–
Input Leakage Current
– 5
2)
Output Leakage Current
1)
The relationship between the
V
DDQ
of the driving device and the
V
REF
of the receiving device is what determines
noise margins. However, in the case of
V
IH (max)
(input overdrive), it is the
V
of the receiving device that is
referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2
outputs (such as a translator), and therefore no
V
DDQ
supply voltage connection, inputs must tolerate input
overdrive to 3.0 V (High corner
V
DDQ
+ 300 mV).
2)
For any pin under test input of 0 V
≤
V
IN
≤
V
DDQ
+ 0.3 V.
– 5
5
2)
Operating, Standby and Refresh Currents (for reference only)
(values apply to one SDRAM component and do not include register and PLL)
(
T
A
= 0 to +70
°
C,
V
DD
= 2.5 V ± 0.2 V)
Parameter
Symbol Test Condition
Speed
Unit Notes
– 7
– 7.5 – 8
Operating Current
t
RC
=
t
RC(min)
,
t
CK
= min.
Active-Precharge
command without burst
operation
I
CC1
1 bank operation
CAS Latency = 2
100
90
70
mA
1), 2), 3)
Precharge Standby
Current in Power Down
Mode
I
CC2P
CKE
≤
V
IL(max)
,
t
CK
= min.,
CS =
V
IH(min)
20
20
20
mA
1)
相關(guān)PDF資料 |
PDF描述 |
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| HYS 72D64020GU | 2.5 V 186-pin Unbuffered DDR-I SDRAM Modules(2.5 V 184腳、寄存型512M位 DDR-I SDRAM 模塊) |
| HYS 64V16220GDL | 3.3V SDRAM Modules(3.3V SDRAM 模塊) |
| HYS 64V16300GU | 3.3 V 16M × 64-Bit 1 Bank SDRAM Module(3.3 V 16M × 64-位 1列 同步動(dòng)態(tài)RAM模塊) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D32000GU-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256MB (32Mx72) PC2100 1-bank? |
| HYS72D32000GU-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D32000GU-7F-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D32000GU-8-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256MB (32Mx72) PC1600 1-bank End-of-Life? |
| HYS72D32000GU-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
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