參數(shù)資料
型號: HYS 72V16220GU
廠商: SIEMENS AG
英文描述: 3.3 V 16M × 64-Bit × 2 Bank同步動態(tài)DRAM Module(3.3 V 16M × 64-位 × 2列同步動態(tài)RAM模塊)
中文描述: 3.3伏1,600 × 64位× 2行同步動態(tài)內(nèi)存(3.3伏1,600 × 64 -位× 2列同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 15/17頁
文件大小: 115K
代理商: HYS 72V16220GU
HYS 64/72V8300/16220GU
SDRAM-Modules
Data Book
15
12.99
25
Minimum Clock Cycle Time
at CL = 1
Maximum Data Access
Time from Clock at CL = 1
Minimum Row Precharge
Time
Minimum Row Active to
Row Active delay
t
RRD
Minimum RAS to CAS
delay
t
RCD
Minimum RAS Pulse Width
t
RAS
Module Bank Density
(per bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Hold
Time
SDRAM Data Input Setup
Time
Superset Information (may
be used in future)
SPD Revision
Checksum for Bytes 0 - 62
64-125 Manufacturers Information –
126
Frequency Specification
127
100 MHz Support Details
128+
Unused Storage Locations
not supported
FF
FF
FF
FF
26
not supported
FF
FF
FF
FF
27
20/30 ns
14
14
14
14
28
16/20 ns
10
10
10
10
29
20 ns
14
14
14
14
30
45 ns
2D
2D
2D
2D
31
64 MByte
10
10
10
10
32
33
34
2 ns
1 ns
2 ns
20
10
20
20
10
20
20
10
20
20
10
20
35
1 ns
10
10
10
10
62-61
FF
FF
FF
FF
62
63
Revision 1.2
12
E0
XX
64
AF
FF
12
F2
XX
64
AF
FF
12
E1
XX
64
FF
FF
12
F3
XX
64
FF
FF
100 MHz
SPD-Table for PC100 Modules
Byte#
Description
SPD Entry Value
Hex
16M
×
64
-8
8M
×
64
-8
8M
×
72
-8
16M
×
72
-8
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參數(shù)描述
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