參數(shù)資料
型號: HYS 72V32300GR-7.5
廠商: SIEMENS AG
英文描述: 3.3V 256MB SDRAM Module(3.3V 256M位 SDRAM 模塊)
中文描述: 3.3 256MB的內(nèi)存模塊(3.3 256M位內(nèi)存模塊)
文件頁數(shù): 10/19頁
文件大小: 228K
代理商: HYS 72V32300GR-7.5
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Data Book
10
1.00
AC Characteristics (SDRAM Device Specification)
4), 5)
T
A
= 0 to 70
°
C
1)
;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-7.5
min.
max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 (64Mb & 128Mb based mod.)
CAS Latency = 2 (256Mb based modules)
t
CK
7.5
10
12
ns
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2 (64Mb & 128Mb based mod.)
CAS Latency = 2 (256Mb based modules)
f
CK
133
100
83
MHz
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
t
AC
5.4
6
ns
ns
Clock High Pulse Width
t
CH
t
CL
t
T
2.5
ns
Clock Low Pulse Width
2.5
ns
Transition Time
0.5
10
ns
Setup and Hold Parameters
Input Setup Time
t
IS
t
IH
t
SB
t
PDE
t
RCS
1.5
ns
Input Hold Time
0.8
ns
Power Down Mode Entry Time
1
CLK
Power Down Mode Exit Setup Time
1
CLK
Mode Register Setup Time
2
CLK
Common Parameters
Row to Column Delay Time
t
RCD
t
RP
t
RAS
t
RC
t
RRD
t
CCD
20
ns
Row Precharge Time
20
ns
Row Active Time
45
100k
ns
Row Cycle Time
67.5
ns
Activate (a) to Activate (b) Command Period
2
CLK
CAS(a) to CAS(b) Command Period
1
CLK
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