參數(shù)資料
型號(hào): HYS 72V8300GU
廠商: SIEMENS AG
英文描述: 3.3 V 8M × 64-Bit × 1 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 8M × 64-位 × 1列同步動(dòng)態(tài)RAM模塊)
中文描述: 3.3伏800萬× 64位× 1行同步動(dòng)態(tài)內(nèi)存(3.3伏8米× 64 -位× 1列同步動(dòng)態(tài)內(nèi)存模塊)
文件頁數(shù): 9/17頁
文件大?。?/td> 115K
代理商: HYS 72V8300GU
HYS 64/72V8300/16220GU
SDRAM-Modules
Data Book
9
12.99
AC Characteristics
3), 4)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-7.5
PC133-333
-8
PC100-222
min.
max.
min.
max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
7.5
10
10
10
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
f
CK
133
100
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
t
AC
5.4
6
6
6
ns
ns
4), 5)
Clock High Pulse Width
t
CH
t
CL
2.5
3
ns
6)
Clock Low Pulse Width
2.5
3
ns
6)
Setup & Hold Parameters
Input Setup Time
t
IS
t
IH
t
SB
t
PDE
t
RSC
t
T
1.5
2
ns
7)
Input Hold Time
0.8
1
ns
7)
Power Down Mode Entry Time
1
1
CLK
8)
Power Down Mode Exit Setup Time
1
1
CLK
9)
Mode Register Setup Time
2
2
CLK
Transition Time (rise and fall)
1
1
ns
Common Parameters
RAS to CAS Delay
t
RCD
t
RP
t
RAS
t
RC
t
RRD
20
20
ns
Precharge Time
20
20
ns
Active Command Period
45
100k
50
100k
ns
Cycle Time
67.5
70
ns
Bank-to-Bank Delay Time
CAS to CAS Delay Time (same bank)
t
CCD
15
16
ns
1
1
CLK
相關(guān)PDF資料
PDF描述
HYS 64V8300GU 3.3 V 8M × 64-Bit × 1 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 8M × 64-位 × 1列同步動(dòng)態(tài)RAM模塊)
HYS 64V16220GU 3.3 V 16M × 72-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 72-位 × 2列同步動(dòng)態(tài)RAM模塊)
HYS 72V16220GU 3.3 V 16M × 64-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 64-位 × 2列同步動(dòng)態(tài)RAM模塊)
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