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參數(shù)資料
| 型號(hào)： | HYS64-72V2200GU-8 |
| 廠商： | SIEMENS AG |
| 英文描述： | Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:7ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes |
| 中文描述： | 3.3 2米x 64/72-Bit一銀行內(nèi)存模塊3.3 4米× 64/72-Bit 2銀行內(nèi)存模塊 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 104K |
| 代理商： | HYS64-72V2200GU-8 |
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Semiconductor Group
13
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
2Mx64
-8-3
80
08
04
0B
09
2Mx72
-8-3
80
08
04
0B
09
4Mx64
-8-3
80
08
04
0B
09
4Mx72
-8-3
80
08
04
0B
09
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
11
9
5
6
7
8
9
10
11
12
1 / 2
64 / 72
0
LVTTL
10.0 ns
6.0 ns
none / ECC
Self-Refresh,
15.6
μ
s
x8
n/a / x8
t
ccd
= 1 CLK
01
40
00
01
A0
60
00
80
01
48
00
01
A0
60
02
80
02
40
00
01
A0
60
00
80
02
48
00
01
A0
60
02
80
13
14
15
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
08
00
01
08
08
01
08
00
01
08
08
01
16
17
18
19
20
21
1, 2, 4, 8 & full page
2
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
10.0 ns
7.0 ns
not supported
not supported
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
22
23
24
25
26
SDRAM Device Attributes :General
Min. Clock Cycle Time at CAS Latency = 2
Max. data access time from Clock for CL=2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
27
28
30 ns
20 ns
1E
14
1E
14
1E
14
1E
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72V4220GU-8 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS72V2200GU-8 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS64V2200GU-10 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS72V2200GU-10 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| HYS64V4220GU-10 | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS6472V4200GU | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module |
| HYS64-74V8200GU | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| HYS64D128020GBDL-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?1GB (1024Mx64) PC2100 2-bank? |
| HYS64D128020GU-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS64D128020GU-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
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