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參數(shù)資料
| 型號： | HYS6472V16200GU |
| 廠商： | SIEMENS AG |
| 英文描述： | Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:15ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes |
| 中文描述： | 3.3伏16米x 64/72-Bit SDRAM模組3.3伏32M的x 64/72-Bit SDRAM模組3.3伏6400 x 64/72-Bit SDRAM模組 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 84K |
| 代理商： | HYS6472V16200GU |
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Semiconductor Group
11
1998-08-01
Notes
1.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements
assume
t
T
= 1 ns with the AC output load circuit show. Specified
t
AC
and
t
OH
parameters are
measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns
edge rate between 0.8 V and 2.0 V.
2.
3.
4.
5.
6.
If clock rising time is longer than 1 ns, a time (
t
T
/2 – 0.5) ns has to be added to this parameter.
Rated at 1.5 V
If
t
T
is longer than 1 ns, a time (
t
T
– 1) ns has to be added to this parameter.
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
7.
8.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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