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參數(shù)資料
| 型號： | HYS64D16000GU-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Unbuffered DDR SDRAM-Modules |
| 中文描述： | 無緩沖DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大小： | 881K |
| 代理商： | HYS64D16000GU-8-A |
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Data Sheet
21
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Address and control input hold time
t
IH
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
t
RPRE
t
RPRE1.5
t
RPRES
t
RPST
t
RAS
t
RC
0.9
0.9
1.5
0.40
50
70
1.1
1.1
—
0.60
120E+3
—
0.9
NA
NA
0.40
45
65
1.1
t
CK
t
CK
ns
t
CK
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)11)
2)3)4)5)12)
Read preamble setup time
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
0.60
120E+3 ns
—
2)3)4)5)
2)3)4)5)
ns
2)3)4)5)
t
RFC
80
—
75
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
20
20
20
15
—
—
—
—
20
20
20
15
—
—
—
—
ns
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
WR
t
DAL
15
—
15
—
ns
t
CK
2)3)4)5)
(
t
wr
/
t
CK
) + (
t
rp
/
t
CK
)
2)3)4)5)13)
t
WTR
t
WTR1.5
t
XSNR
t
XSRD
t
REFI
1
2
80
200
—
—
—
—
—
7.8
1
—
75
200
—
—
—
—
—
7.8
t
CK
t
CK
ns
t
CK
μ
s
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
2)3)4)5)
2)3)4)5)14)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Table 10
Parameter
AC Timing - Absolute Specifications –8/–7
Symbol
–8
–7
Unit Note/
Test Condition
1)
DDR200
Min.
DDR266A
Min.
Max.
Max.
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相關代理商/技術參數(shù) |
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|---|---|
| HYS64D16000HDL-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
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| HYS64D16001GDL-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
| HYS64D16020GD | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM SO Modules |
| HYS64D16020GDL-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM SO Modules |
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