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參數(shù)資料
| 型號： | HYS64D64020HDL-6-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 200-Pin Small Outline Dual-In-Line Memory Modules |
| 中文描述： | 200引腳小外型雙列直插內(nèi)存模塊 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 780K |
| 代理商： | HYS64D64020HDL-6-B |
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18
18
12
Data Sheet
19
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
Address and control input setup time
t
IS
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time
t
IH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
t
XSNR
Exit self-refresh to read command
Average Periodic Refresh Interval
t
RPRE
t
RPST
t
RAS
t
RC
0.9
0.40
42
60
1.1
0.60
70E+3
—
0.9
0.40
40
55
1.1
0.60
70E+3
—
t
CK
t
CK
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
RFC
72
—
65
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
18
—
—
—
—
15
15
15
10
—
—
—
—
ns
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
WR
t
DAL
15
—
15
—
ns
t
CK
2)3)4)5)
2)3)4)5)11)
t
WTR
1
75
200
—
—
—
—
7.8
1
75
200
—
—
—
—
7.8
t
CK
ns
t
CK
μ
s
2)3)4)5)
2)3)4)5)
t
XSRD
t
REFI
2)3)4)5)
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
Table 10
Parameter
AC Timing - Absolute Specifications –6/–5
(cont’d)
Symbol
–6
–5
Unit
Note/ Test
Condition
1)
DDR333
Min.
DDR400B
Min.
Max.
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HYS64D64020HDL-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:200-Pin Small-Outline Dual-In-Line Memory Modules |
| HYS64D64300GU | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D64300GU-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules |
| HYS64D64300GU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D64300HU-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules |
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