- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370803 > HYS64T64020HM-37-A (INFINEON TECHNOLOGIES AG) Double-Data-Rate-Two SDRAM Micro-DIMM PDF資料下載
參數(shù)資料
| 型號： | HYS64T64020HM-37-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Double-Data-Rate-Two SDRAM Micro-DIMM |
| 中文描述： | 雙數(shù)據(jù)速率- 2 SDRAM的微型DIMM |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 955K |
| 代理商： | HYS64T64020HM-37-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
Preliminary
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
I
DD
Specifications and Conditions
Data Sheet
20
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
4.1
I
DD
Test Conditions
For testing the
I
DD
parameters, the timing parameters as in
Table 14
are used.
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Table 14
Parameter
IDD Measurement Test Condition
Symbol
-3.7
-5
Unit
PC2-4200-4-4-4
4
3.75
15
60
PC2-3200-3-3-3
3
5
15
60
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
CL
min
t
CKmin
t
RCDmin
t
RCmin
t
CK
ns
ns
ns
t
RRDmin
10
10
ns
t
RASmin
t
RPmin
t
RFCmin
45
15
105
45
15
105
ns
ns
ns
t
REFI
7.8
7.8
μ
s
Table 15
Parameter
ODT current per terminated pin
Symbol min.
typ.
max. Unit
EMRS(1) State
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
I
ODTO
5
2.5
10
5
6
3
12
6
7.5
3.75
15
7.5
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
I
ODTT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS64T64020HM-5-A | Double-Data-Rate-Two SDRAM Micro-DIMM |
| HYS64T64020GDL-37-A | 200-Pin Small Outline Dual-In-Line Memory Module |
| HYS64T64020GDL-5-A | 200-Pin Small Outline Dual-In-Line Memory Module |
| HYS64T64020HDL | 200-Pin Small Outline Dual-In-Line Memory Module |
| HYS64T64020HDL-37-A | 200-Pin Small Outline Dual-In-Line Memory Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64T64020HM-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:214-Pin Micro-DIMM-DDR2-SDRAM Modules |
| HYS64T64020HM-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:214-Pin Micro-DIMM-DDR2-SDRAM Modules |
| HYS64T64020HU | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS64T64020HU-2.5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS64T64020HU-25F-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復。