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參數(shù)資料
| 型號： | HYS64T64020HM-5-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Double-Data-Rate-Two SDRAM Micro-DIMM |
| 中文描述： | 雙數(shù)據(jù)速率- 2 SDRAM的微型DIMM |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 955K |
| 代理商： | HYS64T64020HM-5-A |
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Preliminary
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
I
DD
Specifications and Conditions
Data Sheet
19
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
Self-Refresh Current
CKE
≤
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°
C
max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2) For details and notes see the relevant INFINEON component data sheet
I
DD6
I
DD7
Table 13
Product Type
I
DD
Specification
H
256 MB
1 Rank
×
64
Max.
280
300
16
128
100
52
20
140
340
360
480
24
16
840
H
H
H
256 MB
1 Rank
×
64
Max.
320
360
16
160
120
64
20
160
400
440
520
24
16
880
H
H
H
512 MB
2 Ranks
×
64
Max.
296
316
32
256
200
104
40
280
356
376
496
40
32
856
H
H
H
512 MB
2 Ranks
×
64
Max.
336
376
32
320
240
128
40
320
416
456
536
40
32
896
H
H
Unit
Notes
Organization
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2N
I
DD2Q
I
DD3P(0)
I
DD3P(1)
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
I
DD6
I
DD7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)2)
1) Calculated values from component data. ODT disabled.
I
DD1
,
I
DD4R
, and
I
DD7
are defined with the outputs disabled.
2) For 2-rank modules only: The other rank is in
I
DD2P
Precharge Power-Down Standby Current mode
3) For 2-rank modules only: Both ranks are in the same
I
DD
mode
1)2)
1)
3)
1)
3)
1)
3)
1)
3)
1)
3)
1)
3)
1)2)
1)2)
1)2)
1)
3)
1)
3)
1)2)
Table 12
Parameter
I
DD
Measurement Conditions
1)2)
(cont’d)
Symbol
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