參數(shù)資料
型號: HYS64V1000GS-10
廠商: SIEMENS AG
英文描述: 3.3V 1M x 64-Bit SDRAM Module 3.3V 1M x 72-Bit SDRAM Module
中文描述: 3.3V的100萬個64位SDRAM模塊3.3V的100萬× 72位SDRAM模塊
文件頁數(shù): 8/9頁
文件大小: 68K
代理商: HYS64V1000GS-10
HYS64(72)V1000GS-10/-12/-15
1M x 64/72 SDRAM-Module
Semiconductor Group
8
Serial Presence Detect
A serial presence detect storage device - E
2
PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E
2
PROM device during
module production using a serial presence detect protocol ( I2C synchronous 2-wire bus)
note : *) not decided yet
Byte#
Description
SPD
Entry
Value
128
256
SDRAM
12
8
1
64
72
0
LVTTL
10 ns
12 ns
15 ns
9 ns
11 ns
13 ns
none
ECC
norrmal
15.6
μ
s
*)
*)
*)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
0
1
2
3
4
5
6
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
80
08
04
0C
08
01
40
48
00
01
A0
C0
F0
90
B0
D0
00
02
00
7
8
9
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time
10
SDRAM Access time from
Clock
11
Dimm Config (Error Det/Corr.)
12
Refresh Rate/Type
13
14
15
16
17
18
19
20
SDRAM Module Attributes
SDRAM Device Attributes
SDRAM Device Attributes
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
1
0
0
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
2
01
*)
*)
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