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參數(shù)資料
| 型號： | HYS64V16300GU |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
| 中文描述： | 3.3伏16米x 64/72-Bit 1銀行128MByte SDRAM的模塊3.3伏32M的x 64/72-Bit 2銀行256MB的內存模塊168引腳無緩沖DIMM模塊 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 322K |
| 代理商： | HYS64V16300GU |
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Technologies
11
9.01
Notes
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100
s is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have
V
IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH and VIL. All AC measurements assume
t
T = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (
t
T/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If
t
T is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to
t
RC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information about the
module configuration, speed, etc. is written into the E
2PROM device during module production using a Serial
Presence Detect protocol (I
2C synchronous 2-wire bus).
50 pF
I/O
Measurement conditions for
t
AC and tOH
CLOCK
2.4 V
0.4 V
INPUT
IS
t
tT
OUTPUT
1.4 V
t LZ
AC
t
tAC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64V16300GU-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V16300GU-7.5-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
| HYS64V16300GU-75-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
| HYS64V16300GU-7-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
| HYS64V16300GU-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
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