參數(shù)資料
型號: HYS64V8220GCDL
廠商: SIEMENS AG
英文描述: 3.3V SDRAM Modules(3.3V SDRAM 模塊)
中文描述: 3.3V的內(nèi)存模塊(3.3V的內(nèi)存模塊)
文件頁數(shù): 8/18頁
文件大?。?/td> 133K
代理商: HYS64V8220GCDL
HYS 64Vx20(2)0GCDL
144-pin SO-DIMM SDRAM Modules
Data Book
8
12.99
Notes
1. These parameters depend on the cycle rate. These values are measured at 100 MHz operation
frequency. Input signals are changed once during
t
CK
, excepts for
I
CC6
and for stand-by currents
when
t
CK
= infinity.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the
V
DDQ
current is excluded.
Operating Currents per Memory Bank
T
A
= 0 to 70
°
C,
V
DD
= 3.3 V
±
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition Symbol
4
8
1
Unit Note
Operating current
t
RC
=
t
RC(MIN.)
,
t
CK
=
t
CK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
I
CC1
260 520
1024 mA
1)
Precharge stand-by current
in Power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
t
CK
= min.
t
CK
= infinity
I
CC2P
I
CC2PS
4
8
16
mA
1)
2
4
8
mA
1)
CS =
V
IH (MIN.)
, CKE
V
IH(MIN.)
No operating current
t
CK
= min.
t
CK
= infinity
I
CC2N
I
CC2NS
70
140
280
mA
1)
10
20
40
mA
1)
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
CKE
V
IH(MIN.)
CKE
V
IL(MAX.)
I
CC3N
I
CC3P
90
180
360
mA
1)
16
32
64
mA
1)
Burst operating current
t
CK
= min.,
Read command cycling
I
CC4
200 400
800
mA
1), 2)
Auto refresh current
t
CK
= min.,
Auto Refresh command cycling
I
CC5
260 520
1040 mA
1)
Self refresh current
Self Refresh Mode, CKE = 0.2 V
I
CC6
1.6
3.2
6.4
mA
1)
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