參數(shù)資料
型號： HYS72T256020GR
廠商： INFINEON TECHNOLOGIES AG
英文描述： DDR2 Registered Memory Modules
中文描述： 注冊的DDR2內(nèi)存模塊
文件頁數(shù)： 15/33頁
文件大?。?/td> 936K
代理商： HYS72T256020GR
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Data Sheet
Preliminary
15
Rev. 0.85, 2004-04
4.5 I
DD
Measurement Conditions
(V
DD
= 1.8V
±
0.1V; V
DDQ
= 1.8V
±
0.1V)
Symbol
Parameter/Condition
I
DD0
Operating Current
-
One bank Active - Precharge
t
= t
, t
= t
tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control
inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current
-
One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, t
= t
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Precharge Power-Down Current:
All banks idle; CKE is LOW; t
CK
= t
CKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current
: All banks idle; CS is HIGH
;
CKE is HIGH; t
CK
= t
CKmin.;
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
: All banks idle; CS is HIGH;
CKE is HIGH; t
CK
= t
CKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
: All banks open; t
= t
CKE is LOW;
Other control and address inputs are STABLE, Data bus
inputs are FLOATING.
MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current
: All banks open; t
= t
CKE is LOW;
Other control and address inputs are STABLE, Data bus
inputs are FLOATING.
MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
: All banks open; t
CK
= t
CKmin.;
t
RAS
= t
RASmax
; tRP = tRPmin.,CKE is HIGH; CS is high between
valid commands.
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Operating Current - Burst Read:
All banks open;
Continuous burst reads; BL = 4;
t
CK
= t
CKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0mA.
Operating Current - Burst Write:
All banks open;
Continuous burst writes; BL = 4;
t
CK
= t
CKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
I
DD1
I
DD2P
I
DD2N
I
DD2Q
I
DD3P(0)
I
DD3P(1)
I
DD3N
I
DD4R
I
DD4W
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Auto-Refresh Current
: t
CK
= t
CKmin.,
Refresh command every t
RFC
= t
RFCmin. interval, CKE is HIGH,
CS is HIGH
between valid commands,
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current
: t
CK
= t
CKmin.,
Refresh command every t
RFC
= t
REFI interval, CKE is LOW and
CS is HIGH
between valid commands,
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
: CKE
≤
0.2V; external clock off, CK and CK at 0V;
Other control and address inputs are FLOATING, Data bus
inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address
bus inputs are STABLE during DESELECTS. Iout = 0mA.
2. Timing pattern:
-
DDR2 -400
: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-
DDR2 -533
: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-
DDR2 -667
: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
I
DD5B
I
DD5D
I
DD6
I
DD7
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes.
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
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相關代理商/技術參數(shù)
參數(shù)描述
HYS72T256020GR-37-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T256020GR-5-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
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