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參數(shù)資料
| 型號： | HYS72T32000GR-37-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DDR2 Registered DIMM Modules |
| 中文描述： | 注冊的DDR2內(nèi)存模組 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 725K |
| 代理商： | HYS72T32000GR-37-A |
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
INFINEON Technologies
14
2.04
4.4 I
DD
Measurement Conditions
Symbol
Parameter/Condition
I
DD0
Operating Current
-
One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD1
Operating Current
-
One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD),tRCD = tRCD(IDD),AL = 0, CL = CL(IDD);
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
I
DD2P
Precharge Power-Down Current:
All banks idle; CKE is LOW; tCK = tCK(IDD);
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I
DD2N
Precharge Standby Current
: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD);
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD2Q
Precharge Quiet Standby Current
: All banks idle; CS is HIGH;
CKE is HIGH; tCK = tCK(IDD);
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I
DD3P(0)
Active Power-Down Current
: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STA-
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
I
DD3P(1)
Active Power-Down Current
: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STA-
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
I
DD3N
Active Standby Current
: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD); tRP = tRP(IDD),CKE is HIGH; CS is high
between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD4R
Operating Current - Burst Read:
All banks open;
Continuous burst reads; BL = 4;AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
I
DD4W
Operating Current - Burst Write:
All banks open;
Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
I
DD5B
Burst Auto-Refresh Current
: tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is
HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5D
Distributed Auto-Refresh Current
: tCK = tCK(IDD), Refresh command every tRFC = tREFI interval, CKE is LOW and CS
is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
: CKE
≤
0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low.
DD6 current values are guaranteed up to TCASE of 85
o
C max.
All Bank Interleave Read Current:
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is high between valid commands, Address bus
inputs are STABLE during DESELECTS; Data bus is SWITCHING.
2. Timing pattern:
-
DDR2 -400
: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-
DDR2 -533
: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-
DDR2 -667
: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
I
DD6
I
DD7
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or
strobes.
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level
the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T32000GR-3-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules |
| HYS72T32000GR-5-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules |
| HYS72T32000HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-2.5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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