參數(shù)資料
型號(hào): HYS72T64000GU-37-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: 240-Pin Unbuffered DDR2 SDRAM Modules
中文描述: 240針無緩沖DDR2 SDRAM內(nèi)存模塊
文件頁數(shù): 9/67頁
文件大?。?/td> 1527K
代理商: HYS72T64000GU-37-A
SSTL
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Data Sheet
9
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
1.3
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in
Table 5
(240 pins). The
abbreviations used in columns Pin and Buffer Type are explained in
Table 6
and
Table 7
respectively. The pin
numbering is depicted in
Figure 1
for non-ECC modules (
×
64) and
Figure 2
for ECC modules
72).
Table 5
Pin#
Pin Configuration of UDIMM
Name
Pin
Type
Buffer
Type
Function
Clock Signals
185
137
220
186
138
221
52
171
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signals 2:0
Complement Clock Signals 2:0
Clock Enable Rank 0
Clock Enable Rank 1
Note:2 Ranks module
Note:1 Rank module
NC
NC
Control Signals
193
76
S0
S1
I
I
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note:2 Ranks module
Note:1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
RAS
CAS
WE
NC
I
I
I
SSTL
SSTL
SSTL
192
74
73
Address Signals
71
190
54
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Bank Address Bus 2
Note:greater than 512Mb DDR2 SDRAMS
Note:less than 1Gb DDR2 SDRAMS
Address Bus 12:0
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
188
183
63
182
61
60
180
58
179
177
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