參數(shù)資料
型號(hào)： HYS72T64000HR-5-A
廠商： INFINEON TECHNOLOGIES AG
英文描述： DDR2 Registered Memory Modules
中文描述： 注冊(cè)的DDR2內(nèi)存模塊
文件頁(yè)數(shù)： 28/67頁(yè)
文件大小： 1527K
代理商： HYS72T64000HR-5-A
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Data Sheet
28
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
5
Electrical Characteristics & AC Timings
5.1
AC Timing Parameter by Speed Grade (Component level data, for reference only)
Table 21
Symbol Parameter
AC Timing - Absolute Specifications –5 / –3.7
–5
DDR2–400
min.
600
2
0.45
5000
5000
3
0.45
–3.7
DDR2–533
min.
-500
2
0.45
5000
3750
3
0.45
WR+
t
RP
-
t
IS
+
t
CK
+
t
IH
350
0.35
450
0.35
WL
-0.25
-
Unit Notes
max.
+
600
-
0.55
8000
8000
-
0.55
-
-
max.
+500
-
0.55
8000
8000
-
0.55
t
AC
t
CCD
t
CH
t
CK
DQ output access time from CK/CK
CAS A to CAS B Command Period
CK, CK high-level width
Clock cycle time
ps
t
CK
t
CK
ps
ps
t
CK
t
CK
t
CK
ns
1)
1)
1)
1)2)
1)3)
t
CKE
t
CL
t
DAL
t
DELAY
CKE minimum high and low pulse width
CK, CK low-level width
Auto precharge write recovery + precharge time WR+
t
RP
Minimum time clocks remain ON after CKE
asynchronously drops low
DQ and DM input hold time
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
Write command to 1st DQS latching transition
1)
1)
1)
t
IS
+
t
CK
+
t
I
H
400
0.35
500
0.35
WL -
0.25
-
-
1)
t
DH
t
DIPW
t
DQSCK
t
DQSL,H
t
DQSS
-
-
+
500
-
WL
+0.25
350
-
-
+
450
-
WL
+0.25
300
ps
t
CK
ps
t
CK
t
CK
1)4)
1)
1)
1)
1)
t
DQSQ
DQS-DQ skew
(for DQS & associated DQ signals)
DQ and DM input setup time
DQS falling edge hold time from CLK
(write cycle)
DQS falling edge to CLK setup time
(write cycle)
Clock Half Period
Data-out high-impedance time from CK/CK
Address and control input hold time
Control and Addr. input pulse width (each input) 0.6
Address and control input setup time
DQ low-impedance from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay (with and without
Auto-Precharge) delay
ps
1)
t
DS
t
DSH
400
0.2
-
-
350
0.2
-
-
ps
t
CK
1)4)
1)
t
DSS
0.2
-
0.2
-
t
CK
1)
t
HP
t
HZ
t
IH
t
IPW
t
IS
t
LZ(DQ)
t
LZ(DQS)
t
MRD
t
OIT
t
RAS
t
RC
t
RCD
min. (t
CL,
t
CH)
-
600
min. (t
CL,
t
CH)
-
600
0.6
600
2*
t
ACmin
t
ACmin
2
0
45
60
15
1)
t
ACmax
-
-
-
t
ACmax
t
ACmax
-
12
70000
-
-
t
ACmax
-
-
-
t
ACmax
t
ACmax
-
12
70000
-
-
ps
ps
t
CK
ps
ps
ps
t
CK
ns
ns
ns
ns
1)
1)4)
1)
600
2*
t
ACmin
t
ACmin
2
0
40
55
15
1)4)
1)
1)
1)
1)
1)
1)
1)
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參數(shù)描述
HYS72T64000HR-5-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64000HU 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T64000HU-2.5-B 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
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