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參數(shù)資料
| 型號(hào)： | I74F50728N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
| 中文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | I74F50728N |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
7
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
°
C
T
amb
= 0
°
C to
+70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
T
amb
= –40
°
C to +85
°
C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
C
L
= 50pF,
R
L
= 500
MIN
TYP
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
UNIT
CONDITION
MAX
MAX
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
Waveform 1
1.5
1.5
2.0
2.0
2.0
2.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
Waveform 1
0.0
0.0
1.5
1.5
1.5
1.5
ns
t
w
(H)
t
w
(L)
t
w
(L)
CPn pulse width,
high or low
Waveform 2
3.0
4.0
3.5
5.0
4.0
5.5
ns
SDn, RDn pulse width, low
Waveform 2
4.5
4.0
4.5
ns
t
rec
Recovery time
SDn, RDn to CPn
Waveform 3
3.5
3.5
3.5
ns
AC WAVEFORMS
V
M
V
M
CPn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(H)
t
h
(H)
Jn, Kn
Qn
V
M
t
w
(H)
1/f
max
t
su
(L)
t
h
(L)
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SF00139
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
SDn or RDn
V
M
V
M
t
rec
CPn
SF00603
Waveform 3. Recovery time for set or reset to output
V
M
V
M
RDn
V
M
Qn
V
M
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SDn
V
M
V
M
t
w
(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
V
M
V
M
t
sk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
NOTES:
For all waveforms, V
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| I74F50729DB | Dual D-Type Flip-Flop |
| I74F50729D-T | Dual D-Type Flip-Flop |
| I74F50729N-B | Dual D-Type Flip-Flop |
| I74F50729D | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729N | RES,FIXED,MF,243 OHM,1%,0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| I74F50728N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
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