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| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 9/64頁 |
| 文件大?。?/td> | 851K |
| 代理商： | I960 VH |
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80960VH
Preliminary
Datasheet
9
2.1
Key Functional Units
2.1.1
DMA Controller
The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents
and 80960 local memory. Two separate DMA channels accommodate data transfers for the primary
PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable
only through the i960 core processor.
2.1.2
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960VH local
memory. The 80960VH has direct access to the PCI bus. The ATU supports transactions between
PCI address space and 80960VH address space.
Address translation is controlled through programmable registers accessible from the PCI interface
and the 80960 core. Dual access to registers allows flexibility in mapping the two address spaces.
2.1.3
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the 80960VH. It
uses interrupts to notify each system when new data arrives. The MU has two messaging
mechanisms. Each allows a host processor or external PCI device and the 80960VH to
communicate through message passing and interrupt generation. The two mechanisms are Message
Registers and Doorbell Registers.
2.1.4
Memory Controller
The Memory Controller allows direct control of external memory systems, including DRAM,
SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically
does not require external logic. It features programmable chip selects, a wait state generator and
byte parity. External memory can be configured as PCI addressable memory.
2.1.5
Core and Peripheral Unit
The Core and Peripheral Unit allows software to control the 80960VH through the primary PCI
bus. For example, the 80960 processor core and the 80960VH local bus can be reset via the PCI
bus.
2.1.6
I
2
C Bus Interface Unit
The I
2
C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and
slave device residing on the I
2
C bus. The I
2
C bus is a serial bus developed by Philips
Semiconductor consisting of a two pin interface. The bus allows the 80960VH to interface to other
I
2
C peripherals and microcontrollers for system management functions. It requires a minimum of
hardware for an economical system to relay status and reliability information on the I/O subsystem
to an external device. For more information, see
I
2
C Peripherals for Microcontrollers
(Philips
Semiconductor).
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