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參數(shù)資料
| 型號： | IA82050-PDW28I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 0K |
| 描述： | IC ASYNCHRONOUS SERIAL CTRL |
| 標(biāo)準(zhǔn)包裝： | 325 |
| 系列： | * |
IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
IA211030617-08
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 12 of 22
1-888-824-4184
Table 4. Line Configure Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DLAB
SBK
PM2
PM1
PM0
SBL0
CL1
CL0
DLAB
– Divisor Latch Access Bit (see Register Summary table)
SBK
– Set Break (0=normal TXD operation, 1=TXD held low – break condition)
PM2, PM1, PM0
– Parity Mode
XX0=No Parity
001=Odd Parity
011=Even Parity
101=High Parity
111=Low Parity
SBL0
– Stop Bit Length
0 = 1 stop bit
1 = 2 stop
CL1, CL0
– Character Length
00=5 Bits
01=6 Bits
10=7 Bits
11=8 Bits
4.5
Line Status Register (LSR)
Reports status of serial link (compatible with 8250). BKD, FE, PE, and OE are cleared when
read. Writing a zero to RFIR acknowledges the interrupt (ADDR 101, Mode R/W, Default
01100000).
Table 5. Line Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
TXST
TFST
BKD
FE
PE
OE
RFIR
TXST
Transmitter Status (1=TX idle or disabled, 0=TX busy)
TFST
Transmit FIFO Status (1=TX FIFO empty, 0=full)
BKD
Break Detected (1=break detected, 0=no break detected)
FE
Framing Error (1=framing error, 0=no framing error)
PE
Parity Error (1=parity error, 0=no parity error)
OE
Overrun Error (1=overrun error, 0=no overrun error)
RFIR
Receive FIFO Interrupt Request (1=RX FIFO full, 0=empty)
4.6
Modem Control Register (MCR)
Drives the general purpose outputs that may be used as modem control discretes. (ADDR 100,
Mode R/W;W, Default 00000000)
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