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參數(shù)資料
| 型號： | IBM04364ARLAD-5N |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 517K |
| 代理商： | IBM04364ARLAD-5N |
IBM04184ARLAD
IBM04364ARLAD
Preliminary
128K x 36 & 256K x 18 SRAM
75H4338
Revised 2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 22
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the
RAM core.
In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary
Scan register, Bypass register and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST
signal is not required.
Signal List
TCK: Test Clock
TMS: Test Mode Select
TDI:
Test Data In
TDO: Test Data Out
Caution: : TCK, TMS, TDI inputs must be placed to a valid logic level, even if JTAG is not used.
TCK tied off will not allow any data to be clocked in, however.
JTAG Recommended DC Operating Conditions (TA=0 to 85°C)
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
JTAG Input High Voltage
VIH1
2.2
—
VDD+0.3
JTAG Input Low Voltage
VIL1
-0.3
—
0.8
V
JTAG Output High Level
VOH1
2.4
—
V
JTAG Output Low Level
VOL1
—
0.4
V
JTAG Input Leakage Current
(VIN = VSS or VDD)
IJTAG
—
+50
A
1. All JTAG inputs/outputs are LVTTL compatible only.
2. IOH1 = -8mA at 2.4V.
3. IOL1 = +8mA at 0.4V.
4. If JTAG is not used, signals TCK, TMS and TDI may be left floating. These inputs are defaulted to VDD with the use of weak active
devices.
JTAG AC Test Conditions (TA=0 to +85°C, VDD=3.3V ±5%)
Parameter
Symbol
Conditions
Units
Notes
Input Pulse High Level
VIH1
3.0
V
Input Pulse Low Level
VIL1
0.0
V
Input Rise Time
TR1
2.0
ns
Input Fall Time
TF1
2.0
ns
Input and Output Timing Reference Level
1.5
V
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