參數(shù)資料
型號(hào)： IBM13N16644HCC
廠商： IBM Microeletronics
英文描述： 16M x 64 Two-Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 1,600 × 64雙行緩沖內(nèi)存模組（16米x 64 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 378K
代理商： IBM13N16644HCC
IBM13N16644HCC
IBM13N16734HCC
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 20
19L7296.E93875B
12/99
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0 - CK3
Input
Pulse
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
CKE0, CKE1
Input
Level
Active
High
Activates the SDRAM CLK signals when high and deactivates them when low. By deacti-
vating the clocks, CKE0/CKE1 low initiates the Power Down mode, Suspend mode, or
the Self Refresh mode.
S0 - S3
Input
Pulse
Active Low
Enables the associated SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active LowWhen sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
BA0, BA1
Input
Level
—
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-
charge.
DQ0 - DQ63,
CB0 - CB7
Input
Output
Level
—
Data and Check Bit Input/Output pins operate in the same manner as on conventional
DRAMs.
DQMB0 -
DQMB7
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the Write operation
if DQM is high.
SA0 - SA2
Input
Level
—
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
Input
Output
Level
—
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
SCL
Input
Pulse
—
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
WP
Input
Level
Active
High
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
V
DD
, V
SS
Supply
Power and ground for the module.
相關(guān)PDF資料
PDF描述
IBM13N16734HCC 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
IBM14M32646BAA-12 x64 SRAM Module
IBM14M32724FPA-11 x72 Linear Burst Mode SRAM Module
IBM14M32724FPA-9 x72 Linear Burst Mode SRAM Module
IBM14M64724DAA-9 x72 Linear Burst Mode SRAM Module
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM14H5481 制造商:AVED Memory Products 功能描述:
IBM14H5540 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述:
IBM17R8251 制造商:AVED Memory Products 功能描述:
IBM17R8252 制造商:AVED Memory Products 功能描述:
IBM1805T 制造商:Schneider Electric 功能描述:IBM1805T
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*