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參數(shù)資料
| 型號(hào)： | IBM13N16734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 1,600 × 72雙行緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | IBM13N16734HCC |
IBM13N16644HCC
IBM13N16734HCC
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 20
19L7296.E93875B
12/99
Clock and Clock Enable Parameters
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CK3
t
CK2
t
AC3 (A)
t
AC2 (A)
t
AC3 (B)
t
AC2 (B)
t
CKH
t
CKL
t
CES
t
CEH
t
SB
t
T
Clock Cycle Time, CAS Latency = 3
10
1000
10
1000
10
1000
ns
Clock Cycle Time, CAS Latency = 2
10
1000
15
1000
15
1000
ns
1
Clock Access Time, CAS Latency = 3
—
—
—
—
—
7
ns
2
Clock Access Time, CAS Latency = 2
—
—
—
—
—
8
ns
2
Clock Access Time, CAS Latency = 3
—
6
—
6
—
9
ns
3
Clock Access Time, CAS Latency = 2
—
6
—
9
—
9
ns
3
Clock High Pulse Width
3
—
3
—
3
—
ns
4
Clock Low Pulse Width
3
—
3
—
3
—
ns
4
Clock Enable Set-up Time
2
—
2
—
3
—
ns
Clock Enable Hold Time
1
—
1
—
1
—
ns
Power down mode Entry Time
0
10
0
10
0
10
ns
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1. For -360 sort, 66Mhz clock: CAS Latency = 2.
2. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 4, 5 and load circuit A.
3. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 6, 7 and load circuit B.
4. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Common Parameters
Symbol
Parameter
-260
-36
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CS
t
CH
Command Setup Time
2
—
2
—
3
—
ns
Command Hold Time
1
—
1
—
1
—
ns
t
AS
Address and Bank Select Set-up
Time
2
—
2
—
3
—
ns
t
AH
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
Address and Bank Select Hold Time
1
—
1
—
1
—
ns
RAS to CAS Delay
20
—
20
—
30
—
ns
1
Bank Cycle Time
70
—
70
—
90
—
ns
1
Active Command Period
50
100000
50
100000
60
100000
ns
1
Precharge Time
20
—
20
—
30
—
ns
1
Bank to Bank Delay Time
20
—
20
—
20
—
ns
1
CAS to CAS Delay Time
1
—
1
—
1
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
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