- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67682 > IBM25NPE405L-3DA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 PDF資料下載
參數(shù)資料
| 型號： | IBM25NPE405L-3DA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | IBM25NPE405L-3DA200CZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Advance Information
PowerNPTM NPe405L Embedded Processor Data Sheet
32
IICSCL
IIC Serial Clock.
I/O
5V tolerant
3.3V LVTTL
1, 2
IICSDA
IIC Serial Data.
I/O
5V tolerant
3.3V LVTTL
1, 2
Interrupts Interface
[IRQ0:6]
Interrupt Requests.
I
5V tolerant
3.3V LVTTL
1, 5
JTAG Interface
TDI
Test Data In.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
Test Mode Select.
I
5V tolerant
3.3V LVTTL
1, 4
TDO
Test Data Out.
O
5V tolerant
3.3V LVTTL
TCK
Test Clock.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
Test Reset.
I
5V tolerant
3.3V LVTTL
2, 5
System Interface
SysClk
Main System Clock input.
I
3.3V Analog
Wire w/ESD
SysReset
Main System Reset.
I/O
5V tolerant
3.3V LVTTL
1, 2
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 4
GPIO0
General Purpose I/O. To access this function, software
must toggle a DCR bit.
I/O
5V tolerant
3.3V LVTTL
1, 6
GPIO1:31
General Purpose I/O. To access this function, software
must toggle a DCR bit.
I/O
5V tolerant
3.3V LVTTL
1
TestEn
Test Enable. Used only for manufacturing tests. Pull down
for normal operation.
I
3.3V LVTTL
Rcvr w/ PD
3
TmrClk
This input must toggle at a rate of less than one half the
CPU core frequency (less than 100MHz in most cases). In
most cases this input toggles much slower (in the 1MHz to
10MHz range).
I
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description (Part 5 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25NPE405L-3FA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA266CZ | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| IBM25PPC405EP-3GB133CZ | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405EP-3GB133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405GP-3DD200C | RISC PROCESSOR, PBGA456 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25NPE405L-3FA133C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。