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| 型號： | IBM25NPE405L-3FA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大小： | 907K |
| 代理商： | IBM25NPE405L-3FA200CZ |
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
47
I/O Specifications—133 and 200MHz (Part 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L
IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and
reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(maximum)
I/O L
(minimum)
Ethernet Interface
EMC0MDClk
n/a
7.4
1.5
12
8
1, async
EMC0MDIO
n/a
8.8
1.2
12
8
EMC0MDClk
1
EMC0TxD0:3
[EMC0Tx0:1D0:1]
[EMC0Tx0:1D]
n/a
10.5
[7.3]
[5.0]
3.0
[2.3]
[1.7]
12
8
PHYTX
1
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
n/a
11.8
[7.2]
[5.6]
2.9
[2.3]
[1.7]
12
8
PHYTX
1
EMC0TxErr[EMC0Tx1En]
n/a
11.8[7.4]
2.9[2.4]
12
8
PHYTX
1
PHY0Col[PHY0Rx1Er]
async[0.2]
async[1.7]
n/a
1
PHY0CrS[PHY0CrS0DV]
async[0.1]
async[1.9]
n/a
1
PHY0RxClk
n/a
1, async
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:1D]
1.5
[0.8]
[0.9]
1.7
[1.7]
[0.3]
n/a
PHYRX
1
PHY0RxDV[PHY0CRS1DV]
1.3[0.7]
1.7[1.7]
n/a
PHYRX
1
PHY0RxErr[PHY0Rx0Er]
1.3[0.7]
1.8[1.9]
n/a
PHYRX
1
PHY0TxClk[PHY0RefClk]
n/a
1, async
HDLCEX Interface
HDLCEXRxClk
n/a
HDLCEXRxDataA:B
23.8
2.1
n/a
HDLCEXRxFS
24.2
1.1
n/a
HDLCEXTxClk
n/a
HDLCEXTxDataA:B
n/a
10.5
3.3
12
8
HDLCEXTxFS
20.3
1.0
n/a
[HDLCEXTxEnA]
n/a
11.3
3.5
12
8
[HDLCEXTxEnB]]
n/a
11.8
3.8
12
8
Trace Interface
[TrcClk]GPIO00
n/a
11.2
1.2
12
8
[TS1E]GPIO01
n/a
7.0
1.2
12
8
[TS2E]GPIO02
n/a
7.0
1.2
12
8
[TS1O]GPIO03
n/a
6.5
1.0
12
8
[TS2O]GPIO04
n/a
6.4
1.0
12
8
[TS3:6]GPIO05:08
n/a
6.4
1.0
12
8
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