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參數(shù)資料
| 型號(hào)： | IBM25PPC405GPR3BB400Z |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 X 35 MM, ENHANCED, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 2/58頁 |
| 文件大?。?/td> | 1264K |
| 代理商： | IBM25PPC405GPR3BB400Z |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Page 10 of 58
3/14/03
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
Programmable address mapping
Peripheral Device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
Four channels
Scatter/gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
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