參數(shù)資料
型號: IBM25PPC750L-GB366A2R
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 366 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 15/48頁
文件大?。?/td> 608K
代理商: IBM25PPC750L-GB366A2R
Page 22
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
IEEE 1149.1 AC Timing Specications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
JTAG AC Timing Specications (Independent of SYSCLK)
L = 50pF.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
ns
2
TCK clock pulse width measured at 1.4V
15
ns
3
TCK rise and fall times
0
2
ns
4
spec obsolete, intentionally omitted
5
TRST assert time
25
ns
6
Boundary-scan input data setup time
4
ns
7
Boundary-scan input data hold time
16
ns
8
TCK to output data valid
4
20
ns
9
TCK to output high impedance
3
19
ns
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
16
ns
12
TCK to TDO data valid
2.5
12
ns
13
TCK to TDO high impedance
3
9
ns
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9. JTAG Clock Input Timing Diagram
1
2
3
VM
TCK
VM
Vm = 1.4 V for OVdd = 3.3 V., else Vm = OVdd/2
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