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| 型號： | IBMB3N16734HCB-260 |
| 英文描述： | x72 SDRAM Module |
| 中文描述： | x72內(nèi)存模塊 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | IBMB3N16734HCB-260 |
IBM13N16644HCC
IBM13N16734HCC
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
19L7296.E93875B
12/99
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
Data in Hold Time
0
μ
s
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The Write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle.
During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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