參數(shù)資料
型號(hào): IC41C44002-60JI
英文描述: 4Mx4 bit Dynamic RAM with EDO Page Mode
中文描述: 4Mx4位動(dòng)態(tài)RAM與江戶頁面模式
文件頁數(shù): 19/20頁
文件大?。?/td> 236K
代理商: IC41C44002-60JI
IC41C4400x and IC41LV4400x Series
8
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-
50
-
60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tACH
Column-Address Setup Time to
CAS
15
15
ns
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
8
10
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
0
0
ns
tDH
Data-In Hold Time(15, 22)
8
10
ns
tRWC
READ-MODIFY-WRITE Cycle Time
108
133
ns
tRWD
RAS to WE Delay Time during
64
77
ns
READ-MODIFY-WRITE Cycle(14)
tCWD
CAS to WE Delay Time(14, 20)
26
32
ns
tAWD
Column-Address to
WE Delay Time(14)
39
47
ns
tPC
EDO Page Mode READ or WRITE
20
25
ns
Cycle Time
tRASP
RAS Pulse Width in EDO Page Mode
50
100K
60
100K
ns
tCPA
Access Time from
CAS Precharge(15)
30
35
ns
tPRWC
EDO Page Mode READ-WRITE
56
68
ns
Cycle Time
tCOH
Data Output Hold after
CAS LOW
5
5
ns
tOFF
Output Buffer Turn-Off Delay from
0
12
0
15
ns
CAS or RAS(13,15,19, 24)
tWHZ
Output Disable Delay from
WE
310
3
10
ns
tCSR
CAS Setup Time (CBR REFRESH)(20, 25)
5
5
ns
tCHR
CAS Hold Time (CBR REFRESH)( 21, 25)
8
10
ns
tORD
OE Setup Time prior to RAS during
0
0
ns
HIDDEN REFRESH Cycle
tREF
Auto Refresh Period
2,048 Cycles
32
32
ms
4,096 Cycles
64
64
tT
Transition Time (Rise or Fall)(2, 3)
150
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
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