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參數(shù)資料
| 型號： | IC41C8512-35TI |
| 英文描述： | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| 中文描述： | 為512k × 8位動態(tài)隨機(jī)存儲器與江戶頁面模式 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 232K |
| 代理商： | IC41C8512-35TI |
IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
7
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
–10
10
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
–10
10
μA
V
OH
Output High Voltage Level
I
OH
= –2.5 mA
2.4
—
V
V
OL
Output Low Voltage Level
I
OL
=+2.1mA
—
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
≥
V
IH
5V
3.3V
—
—
2
mA
0.5
I
CC
2
Standby Current: CMOS
RAS
,
CAS
≥
V
CC
– 0.2V
5V
3.3V
—
—
1
mA
0.5
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
CAS
,
Address Cycling, t
RC
= t
RC
(min.)
-35
-50
-60
—
—
—
120
110
100
mA
I
CC
4
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
CAS
,
Cycling t
PC
= t
PC
(min.)
-35
-50
-60
—
—
—
100
90
80
mA
I
CC
5
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
RAS
Cycling,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
-35
-50
-60
—
—
—
120
110
100
mA
I
CC
6
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
CAS
Cycling
t
RC
= t
RC
(min.)
-35
-50
-60
—
—
—
120
110
100
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC41C8512-60T | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-60TI | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-50T | 10:1 LVDS Serdes Transmitter 100-400 Mbps 28-SSOP -40 to 85 |
| IC41LV8512-50TI | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-60K | Replaced by SN65LV1023A : 10:1 LVDS Serdes Transmitter 300-660 Mbps 28-SSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC41C8512-50K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50KI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-60K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
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