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參數(shù)資料
| 型號： | IC41LV16257S-60TI |
| 英文描述： | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| 中文描述： | 256K × 16（4兆位）充滿活力和快速頁面模式內(nèi)存 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 760K |
| 代理商： | IC41LV16257S-60TI |
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
7
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
= –2.5 mA
I
OL
= +2.1 mA
–10
10
μA
I
IO
Output Leakage Current
–10
10
μA
V
OH
V
OL
Output High Voltage Level
Output Low Voltage Level
2.4
—
—
0.4
V
V
I
CC
1
Stand-by Current: TTL
RAS
,
LCAS
,
UCAS
≥
V
IH
Com.
Ind.
Com. 3.3V
Ind. 3.3V
5V
5V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
1
2
1
mA
mA
mA
mA
mA
mA
mA
I
CC
1
Stand-by Current: TTL
RAS
,
LCAS
,
UCAS
≥
V
IH
I
CC
2
I
CC
2
I
CC
3
Stand-by Current: CMOS
Stand-by Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
Fast Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
Self Refresh current
(6)
RAS
,
LCAS
,
UCAS
≥
V
CC
– 0.2V
RAS
,
LCAS
,
UCAS
≥
V
CC
– 0.2V
RAS
,
LCAS
,
UCAS
,
Address Cycling, t
RC
= t
RC
(min.)
5V
3.3V
-35
-50
-60
-35
-50
-60
-35
-50
-60
-35
-50
-60
5V
3.3V
0.5
230
180
170
220
170
160
230
180
170
230
180
170
300
300
I
CC
4
RAS
= V
IL
,
LCAS
,
UCAS
,
Cycling t
PC
= t
PC
(min.)
mA
I
CC
5
RAS
Cycling,
LCAS
,
UCAS
≥
V
IH
t
RC
= t
RC
(min.)
mA
I
CC
6
RAS
,
LCAS
,
UCAS
Cycling
t
RC
= t
RC
(min.)
mA
I
CCS
Self Refresh Mode
μA
μA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured.The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
6. I
CCS
is for S version only.
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