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參數(shù)資料
| 型號： | IC41SV44054-70JG |
| 英文描述： | 4Mx4 bit Dynamic RAM with Fast Page Mode |
| 中文描述： | 4Mx4位動態(tài)RAM的快速頁面模式 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 248K |
| 代理商： | IC41SV44054-70JG |
IC41SV44052
IC41SV44054
8
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-
70
-
100
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
ACH
Column-Address Setup Time to
CAS
Precharge during WRITE Cycle
OE
Hold Time from
WE
during
READ-MODIFY-WRITE cycle
(18)
Data-In Setup Time
(15, 22)
Data-In Hold Time
(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS
to
WE
Delay Time during
READ-MODIFY-WRITE Cycle
(14)
CAS
to
WE
Delay Time
(14, 20)
Column-Address to
WE
Delay Time
(14)
Fast Page Mode READ or WRITE
Cycle Time
Fast Page Mode
RAS
Pulse Width
Access Time from
CAS
Precharge
(15)
Fast Page Mode READ WRITE
Cycle Time
Output Buffer Turn-Off Delay from
CAS
or
RAS
(13,15,19, 24)
CAS
Setup Time (CBR REFRESH)
(20, 25)
CAS
Hold Time (CBR REFRESH)
( 21, 25)
OE
Setup Time prior to
RAS
during
HIDDEN REFRESH Cycle
Auto Refresh Period
2
,0
48
Cycles
Auto Refresh Period 4,096 Cycles
Transition Time (Rise or Fall)
(2, 3)
15
15
ns
t
OEH
20
25
ns
t
DS
t
DH
t
RWC
t
RWD
0
15
185
100
0
20
240
130
ns
ns
ns
ns
t
CWD
t
AWD
t
PC
45
60
45
55
85
60
ns
ns
ns
t
RASP
t
CPA
t
PRWC
70
100
100K
40
100
120
100K
55
ns
ns
ns
t
OFF
3
15
3
15
ns
t
CSR
t
CHR
t
ORD
5
10
0
5
10
0
ns
ns
ns
t
REF
3
32
64
50
3
32
64
50
ms
ms
ns
t
T
AC TEST CONDITIONS
Output load:
One TTL Load and 100 pF
Input timing reference levels:
V
IH
= 1.6V, V
IL
= 0.6V
Output timing reference levels: V
OH
= 1.6V, V
OL
= 0.8V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC41SV44054-70T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4Mx4 bit Dynamic RAM with Fast Page Mode |
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| IC41UV4105-100T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1Mx4 bit Dynamic RAM with Fast Page Mode |
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