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參數(shù)資料
| 型號(hào)： | IC61C1024L-25TI |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 128K的× 8高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 204K |
| 代理商： | IC61C1024L-25TI |
IC61C1024
IC61C1024L
6
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-12
(2)
-15 ns
Min.
-20 ns
Min.
-25 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACE
1
t
ACE
2
t
DOE
t
LZOE
(3)
t
HZOE
(3)
t
LZCE
1
(3)
CE1
to Low-Z Output
t
LZCE
2
(3)
CE2 to Low-Z Output
t
HZCE
(3)
CE1
or CE2 to High-Z Output
t
PU
(4)
CE1
or CE2 to Power-Up
t
PD
(4)
CE1
or CE2 to Power-Down
Parameter
Min.
Max.
Max.
Max.
Max.
Unit
Read Cycle Time
12
—
15
—
20
—
25
—
ns
Address Access Time
—
12
—
15
—
20
—
25
ns
Output Hold Time
3
—
3
—
3
—
3
—
ns
CE1
Access Time
—
12
—
15
—
20
—
25
ns
CE2 Access Time
—
12
—
15
—
20
—
25
ns
OE
Access Time
—
6
—
7
—
9
—
9
ns
OE
to Low-Z Output
0
—
0
—
0
—
0
—
ns
OE
to High-Z Output
0
6
0
6
0
7
0
10
ns
2
—
2
—
3
—
3
—
ns
2
—
2
—
3
—
3
—
ns
0
7
0
8
0
9
0
10
ns
0
—
0
—
0
—
0
—
ns
—
12
—
12
—
18
—
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. -12 ns device for IC61C1024 only.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
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