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參數(shù)資料
| 型號(hào)： | IC61LV12816-8T |
| 英文描述： | 128K x 16 Hight Speed SRAM with 3.3V |
| 中文描述： | 128K的× 16 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 150K |
| 代理商： | IC61LV12816-8T |
IC61LV12816
Integrated Circuit Solution, Inc.
AHSR024-0B
04/23/2004
11
1
2
3
4
5
6
7
8
9
10
11
12
WRITE CYCLE NO. 4
(1,3)
(
LB
,
UB
Controlled, Back-to-Back Write)
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PWB
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PWB
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of
CE
= LOW,
UB
and/or
LB
= LOW, and
WE
= LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
t
SA
,
t
HA
,
t
SD
, and
t
HD
timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with
OE
HIGH for a minimum of 4 ns before
WE
= LOW to place the I/O in a HIGH-Z state.
3.
WE
may be held LOW across many address cycles and the
LB
,
UB
pins can be used to control the Write function.
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| IC61LV12816-8TI | 128K x 16 Hight Speed SRAM with 3.3V |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC61LV12816-8TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 16 Hight Speed SRAM with 3.3V |
| IC61LV256 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10J | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10JG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
| IC61LV256-10JI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K x 8 Hight Speed SRAM with 3.3V |
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