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參數(shù)資料
| 型號： | IC61LV6416-8KI |
| 英文描述： | 64K x 16 Hight Speed SRAM with 3.3V |
| 中文描述： | 64K的× 16 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 95K |
| 代理商： | IC61LV6416-8KI |
IC61LV6416
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
7
1
2
3
4
5
6
7
8
9
10
11
12
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8
-10
-12
-15
Symbol
t
WC
t
SCE
t
AW
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
8
—
10
—
12
—
15
—
ns
CE
to Write End
7
—
8
—
9
—
10
—
ns
Address Setup Time
to Write End
7
—
8
—
9
—
10
—
ns
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
0
—
ns
LB
,
UB
Valid to End of Write
7
—
8
—
9
—
10
—
ns
WE
Pulse Width
7
—
8
—
9
—
10
—
ns
Data Setup to Write End
4.5
—
5
—
6
—
7
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
4
—
5
—
6
—
7
ns
WE
HIGH to Low-Z Output
3
—
3
—
3
—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC61LV6416-8T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 16 Hight Speed SRAM with 3.3V |
| IC61LV6416-8TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 16 Hight Speed SRAM with 3.3V |
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