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參數(shù)資料
| 型號： | IC61LV6416-8TI |
| 英文描述： | 64K x 16 Hight Speed SRAM with 3.3V |
| 中文描述： | 64K的× 16 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 95K |
| 代理商： | IC61LV6416-8TI |
IC61LV6416
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
5
1
2
3
4
5
6
7
8
9
10
11
12
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8
-10
-12
-15
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
t
LZB
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
8
—
10
—
12
—
15
—
ns
Address Access Time
—
8
—
10
—
12
—
15
ns
Output Hold Time
3
—
3
—
3
—
3
—
ns
CE
Access Time
—
8
—
10
—
12
—
15
ns
OE
Access Time
—
4
—
5
—
6
—
7
ns
OE
to High-Z Output
0
4
—
5
—
6
0
6
ns
OE
to Low-Z Output
0
—
0
—
0
—
0
—
ns
CE
to High-Z Output
0
4
0
5
0
6
0
6
ns
CE
to Low-Z Output
3
—
3
—
3
—
3
—
ns
LB
,
UB
Access Time
—
4
—
5
—
6
—
7
ns
LB
,
UB
to High-Z Output
0
4
0
5
0
6
0
6
ns
LB
,
UB
to Low-Z Output
0
—
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Figure 1a.
Figure 1b.
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
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