參數(shù)資料
型號(hào): IC62LV256-100JI
英文描述: 32K x 8 Low Power SRAM with 3.3V
中文描述: 32K的× 8低功耗SRAM與3.3V
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 88K
代理商: IC62LV256-100JI
IC62LV256
Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001
5
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns
-70 ns
-100 ns
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
45
70
100
ns
Address Access Time
45
70
100
ns
Output Hold Time
2
2
2
ns
CE
Access Time
45
70
100
ns
OE
Access Time
25
35
50
ns
OE
to Low-Z Output
0
0
0
ns
OE
to High-Z Output
0
20
0
25
0
25
ns
CE
to Low-Z Output
3
3
3
ns
CE
to High-Z Output
0
20
0
25
0
25
ns
CE
to Power-Up
0
0
0
ns
CE
to Power-Down
30
50
50
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
1213
100 pF
Including
jig and
scope
1378
OUTPUT
3.3V
Figure 1a.
Figure 1b.
1213
5 pF
Including
jig and
scope
1378
OUTPUT
3.3V
相關(guān)PDF資料
PDF描述
IC62LV256-100J 32K x 8 Low Power SRAM with 3.3V
IC62LV256 32K x 8 Low Power SRAM with 3.3V
IC62LV2568L-100B 256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM
IC62LV2568L-100BI 256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM
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