參數(shù)資料
型號: IC62LV256-100T
英文描述: RES 82.5 OHM 1% 1206 1110-0820
中文描述: 32K的× 8低功耗SRAM與3.3V
文件頁數(shù): 3/9頁
文件大小: 88K
代理商: IC62LV256-100T
IC62LV256
Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001
3
PIN CONFIGURATION
28-Pin DIP, SOJ and SOP
PIN CONFIGURATION
8x13.4mm TSOP-1
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
X
CE
H
OE
X
I/O Operation
Vcc Current
Not Selected
(Power-down)
Output Disabled
Read
Write
High-Z
I
SB
1
, I
SB
2
H
H
L
L
L
L
H
L
X
High-Z
D
OUT
D
IN
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
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