參數(shù)資料
型號: ICE2A765P
英文描述: ?max. Pout=130W. fop=100kHz. Vbreak=650V. TO220?
中文描述: ?最大。噘\u003d 130瓦。紈褲子弟\u003d 100kHz的。 Vbreak \u003d?650V。的TO220?
文件頁數(shù): 10/25頁
文件大?。?/td> 642K
代理商: ICE2A765P
Datasheet
Preliminary Data
10
August 2001
Preliminary Specification
CoolSET
-F2
ICE2A765P
ICE2B765P
Functional Description
Figure 11
Start Up Phase
3.4
Oscillator and Frequency
Reduction
3.4.1
Oscillator
The oscillator generates a frequency f
switch
= 67kHz/
100kHz. A resistor, a capacitor and a current source
and current sink which determine the frequency are
integrated. The charging and discharging current of the
implemented
oscillator
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a max. duty cycle limitation
of D
max
=0.72.
capacitor
are
internally
3.4.2
Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
12. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 20kHz / 21.5 kHz to
avoid audible noise in any case.
Figure 12
Frequency Dependence
3.5
Current Limiting
There is a cycle by cycle current limiting realised by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
CoolMOS
TM
is sensed via an external sense resistor
R
. By means of R
the source current is
transformed to a sense voltage V
Sense
. When the
voltage V
Sense
exceeds the internal threshold voltage
V
csth
the Current-Limit-Comparator immediately turns
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immedeate shut down of the
CoolMOS
in case of overcurrent.
3.5.1
Leading Edge Blanking
Figure 13
Leading Edge Blanking
Each time when CoolMOS
is switched on a leading
spike
is
generated
due
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t
LEB
= 220ns. During that time the output of
to
the
primary-side
t
t
V
SoftS
t
5.3V
4.8V
T
Soft-Start
V
OUT
V
FB
V
OUT
T
Start-Up
f
standby
f
norm
1,0
1,1
1,2
1,3
1,4
1,5
1,6
1,7
1,8
1,9
2
F B
V
V
kH z
O
f
f
norm
:
f
standby
:
ICE2B765P
67kHz
20kHz
ICE2A765P
100kHz
21.5kHz
t
V
Sense
V
csth
t
LEB
= 220ns
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ICE2B765P ?max. Pout=130W. fop=67kHz. Vbreak=650V. TO220?
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