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參數(shù)資料
| 型號(hào)： | ICL3310IB-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | +3V to +5.5V, 1 Microamp, 250kbps, RS-232 Transmitter/Receiver |
| 中文描述： | DUAL LINE TRANSCEIVER, PDSO18 |
| 封裝： | PLASTIC, SOIC-18 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 158K |
| 代理商： | ICL3310IB-T |
7
Interconnection with 3V and 5V Logic
The ICL3310 directly interface with most 5V logic families,
including ACT and HCT CMOS. See Table 3 for more
information on possible combinations of interconnections.
FIGURE 7. LOOPBACK TEST AT 120kbps
FIGURE 8. LOOPBACK TEST AT 250kbps
T1
IN
T1
OUT
R1
OUT
5
μ
s/DIV.
V
CC
= +3.3V
C1 - C4 = 0.1
μ
F
5V/DIV.
T1
IN
T1
OUT
R1
OUT
2
μ
s/DIV.
5V/DIV.
V
CC
= +3.3V
C1 - C4 = 0.1
μ
F
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
3.3
Compatible with all CMOS families.
5
5
Compatible with all TTL and CMOS
logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. Incompatible
with AC, HC, or CD4000 CMOS.
Typical Performance Curves
V
CC
= 3.3V, T
A
= 25
o
C
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 10. SLEW RATE vs LOAD CAPACITANCE
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
1000
2000
3000
4000
5000
0
LOAD CAPACITANCE (pF)
T
1 TRANSMITTER AT 250kbps
1 TRANSMITTER AT 30kbps
V
OUT
+
V
OUT
-
LOAD CAPACITANCE (pF)
S
μ
s
0
1000
2000
3000
4000
5000
5
10
15
20
25
+SLEW
-SLEW
ICL3310
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