參數(shù)資料
型號(hào)： ICL7104-14CPL
廠商： HARRIS SEMICONDUCTOR
元件分類： ADC
英文描述： 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter
中文描述： 1-CH 14-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
文件頁(yè)數(shù)： 15/21頁(yè)
文件大小： 198K
代理商： ICL7104-14CPL
5-20
Detailed Description
DIGITAL SECTION
The digital section includes the clock oscillator circuit, a
16-bit or 14-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 9 (16-bit version shown).
Throughout this description, logic levels will be referred to as
“l(fā)ow” or “high”. The actual logic levels are defined under
“ICL7104 Electrical Specification”. For minimum power con-
sumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3 - 5k
pullup resistors added for maximum noise immunity.
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter is
in its “Direct” output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 8 for details of
this timing. This signal may be used as a “data valid” flag
(data never changes while STATUS is low) to drive inter-
rupts, or for monitoring the status of the converter.
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
ICL7104-16
POL
O/R
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
HBEN
LBEN
ICL7104-14
POL
O/R
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
FIGURE 9. DIGITAL SECTION
HBEN
MBEN
(-16 ONLY)
LBEN
CE/LD
OSCILLATOR
AND CLOCK
CIRCUITRY
27
SEND
21
MODE
25
CLOCK
(3)
23
CLOCK
(2)
24
2
STATUS
26
R/H
18/16 THREE-STATE OUTPUTS
18/16 LATCHES
18/16 BIT COUNTER
LATCH
CLOCK
HANDSHAKE
LOGIC
CONVERSION
CONTROL
LOGIC
INITIAL
CLEAR
CLOCK
(1)
COMP OUT
AZ
INT
DEINT(+)
DEINT(-)
TO
ANALOG
SECTION
ICL8052/ICL7104, ICL8068/ICL7104
相關(guān)PDF資料
PDF描述
ICL7104-16CPL 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter
ICL7106 3 1/2 Digital ADC(3 1/2位數(shù)，具有直接液晶顯示驅(qū)動(dòng)器的ADC)
ICL7107 3 1/2 Digital ADC(3 1/2位數(shù)，具有直接液晶顯示驅(qū)動(dòng)器的ADC)
ICL7107CJL 3 Digit A/D Converter
ICL7106-ICL7107 3 Digit A/D Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICL7104-16CDL 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition
ICL7104-16CJL 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition
ICL7104-16CPL 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Precision 4 1/2 Digit, A/D Converter
ICL7106 制造商:ESTEK 制造商全稱:ESTEK 功能描述:True Differential input and Reference, Direct Display
ICL7106_0512 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:3 Digit, LCD/LED Display, A/D Converters
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*