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參數(shù)資料
| 型號(hào)： | ICL7139CPL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Quad LVDS Receiver with -2 to 4.4V Common-mode Range 16-SOIC -40 to 85 |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP40 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 111K |
| 代理商： | ICL7139CPL |
3-37
Detailed Description
General
The Functional Block Diagram shows the digital section
which includes all control logic, counters, and display drivers.
The digital section is powered by V+ and Digital Common,
which is about 3V below V+. The oscillator is also in the digi-
tal section. Normally 120kHz for rejection of 60Hz AC inter-
ference and 100kHz for rejection of 50Hz AC should be
used. The oscillator output is divided by two to generate the
internal master clock. The analog section contains the inte-
grator, comparator, reference section, analog buffers, and
several analog switches which are controlled by the digital
logic. The analog section is powered from V+ and V-.
DC Voltage Measurement
Autozero
Only those portions of the analog section which are used
during DC voltage measurements are shown in Figure 3. As
shown in the timing diagram (Figure 1), each measurement
starts with an autozero (AZ) phase. During this phase, the
integrator and comparator are configured as unity gain buff-
ers and their non-inverting inputs are connected to Common.
The output of the integrator, which is equal to its offset, is
stored on C
AZ
- the autozero capacitor. Similarly, the offset of
the comparator is stored in C
lNT
. The autozero cycle equals
1000 clock cycles which is one 60Hz line cycle with a 120kHz
oscillator, or one 50Hz line cycle with a 100kHz oscillator.
Range 1 Integrate
The ICL7139 and ICL7149 perform a full autorange search
for each reading, beginning with range 1. During the range 1
integrate period, internal switches connect the INT V/
terminal to the Triple Point (Pin 13). The input signal is inte-
grated for 10 clock cycles, which are gated out over a period
of 1000 clock cycles to ensure good normal mode rejection
of AC line interference.
LOW
BATT
DIGIT 3
2
1
0
DP3
DP2
DP1
AC
a
g
b
k
c
mAV
M
μ
A
d
e
f
FIGURE 2. DISPLAY SEGMENT NOMENCLATURE
+
-
+
-
+
-
TRIPLE
POINT
C
AZ
C
INT
R
DEINT
AZ
DEINT-
DEINT-
V
REF
INTEGRATOR
COMPARATOR
TO LOGIC SECTION
6.7V
ANALOG
COMMON
V
IN
R
INTV
INT V/
80
μ
A
C
AZ
C
INT
R
DEINT
AZ
AZ
AZ
COMMON
T
T
DEINT+
DEINT+
V+
V-
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V
REF
FIGURE 3. DETAILED CIRCUIT DIAGRAM FOR DC VOLTAGE MEASUREMENT
ICL7139, ICL7149
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