參數(shù)資料
型號(hào): ICM7211AMLPL
廠商: INTERSIL CORP
元件分類: 顯示驅(qū)動(dòng)器
英文描述: 4-Digit, LCD Display Driver
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 10/12頁
文件大?。?/td> 83K
代理商: ICM7211AMLPL
9-15
elevated temperatures the segment current be limited by use
of the brightness input to keep power dissipation within the
limits described above.
Input Configurations and Output Codes
The standard devices in the ICM7211 and ICM7212 family
accept a four-bit true binary (i.e., positive level = logical one)
input at pins 27 thru 30, least significant bit at pin 27 ascend-
ing to the most significant bit at pin 30. The ICM7211 and
ICM7211M devices decode this binary input into a seven-
segment alphanumeric hexadecimal output, while the
ICM7211A, ICM7211AM, and ICM7212AM decode the
binary input into seven-segment alphanumeric “Code B” out-
put, i.e., 0-9, dash, E, H, L, P, blank. These codes are shown
explicitly in Table 1. Either decoder option will correctly
decode true BCD to a seven-segment decimal output.
These devices are actually mask-programmable to provide
any 16 combinations of the seven segment outputs decoded
from the four input bits. For large quantity orders custom
decoder options can be arranged. Contact the factory for
details.
The ICM7211 and ICM7211A devices are designed to accept
multiplexed binary or BCD input. These devices provide four
separate digit lines (least significant digit at pin 31 ascending
to most significant digit at pin 34), each of which when taken
to a positive level decodes and stores in the output latches of
its respective digit the character corresponding to the data at
the input port, pins 27 through 30.
The ICM7211M, ICM7211AM, and ICM7212AM devices are
intended to accept data from a data bus under processor
control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input buffer
latches when both chip select inputs (CS1 pin 33, CS2 pin
34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the con-
tents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 2, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
TABLE 1. OUTPUT CODES
BlNARY
HEXADECIMAL
ICM7211
ICM7211M
CODE B
ICM7211A
ICM7212AM
B3
B2
B1
BO
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
BLANK
a
b
c
d
f
g
e
FIGURE 10. SEGMENT ASSIGNMENT
ICM7211, ICM7212
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICM7211AMLPLZ 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4-Digit, LCD Display Driver
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