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參數(shù)資料
| 型號： | ICS1493K-17LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 20-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器，扇出配送，擴(kuò)展頻譜時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 48MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -10°C ~ 80°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-VFQFPN（4x4） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1493K-17LFT |
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS
SYNTHESIZERS
IDT / ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS
3
ICS1493-17
REV A 101005
.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS1493-17 must be isolated from system power
supply noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
I2C External Resistor Connection
The SCK and SDATA pins can be connected to any
voltage between 1.71 V and 2.625 V.
Crystal Load Capacitors
No external crystal load capacitors are required. To
save discrete component cost, the ICS1493-17
integrates on-chip capacitance to support a crystal with
CL=10 pF. It is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination resistor
should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS1493-17. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
18
VDD
Power
Connect to +1.8 V.
19
X2
Output
Connect to 27 MHz crystal or float for clock input.
20
X1
Input
Crystal connection. Connect to 27 MHz crystal or clock input.
Pin
Number
Pin
Name
Pin
Type
Pin Description
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