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參數(shù)資料
| 型號(hào)： | ICS1574B |
| 英文描述： | GT 5C 5#12 PIN RECP WALL RM |
| 中文描述： | 用戶可編程的激光引擎像素時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | ICS1574B |
ICS1574B
4
PLL Post-Scaler
A programmable post-scaler may be inserted between the
VCO and the PCLK divider of the
ICS1574B
. This is useful in
generating lower frequencies, as the VCO has been optimized
for high-frequency operation. The post-scaler is not affected
by the PCLKEN input.
The post-scaler allows the selection of:
VCO frequency
VCO frequency divided by 2
VCO frequency divided by 4
AUX-EN Test Mode
PLL Synthesizer Description —
Ratiometric Mode
The
ICS1574B
generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference fre-
quency may be applied to the
ICS1574B
from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or VCO, to a fre-
quency that will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:
back divider makes use of a dual-modulus prescaler tech-
nique that allows the programmable counters to operate at
low speed without sacrificing resolution. This is an improve-
ment over conventional fixed prescaler architectures that
typically impose a factor-of-four (or larger) penalty in this re-
spect.
Table 1 permits the derivation of
“
A
”
&
“
M
”
converter pro-
gramming directly from desired modulus.
Digital Inputs
The programming of the
ICS1574B
is performed serially
by using the DATCLK, DATA, and HOLD pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD pin is latched at
the same time. When HOLD is low, the shift register may
be loaded without disturbing the operation of the
ICS1574B
. When high, the shift register outputs are trans-
ferred to the control registers, and the new programming
information becomes active. Ordinarily, a high level
should be placed on the HOLD pin when the last data bit is
presented. See Figure 3 for the programming sequence.
The PCLKEN input polarity may be programmed under
register control via Bit 39.
F
(VCO)
:
= F(XTAL1)
Feedback Divider
Reference Divider
Figure 3
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency pro-
vided to the part (assuming correctly programmed dividers).
The VCO gain is programmable, permitting the
ICS1574B
to
be optimized for best performance at all operating frequen-
cies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 392 in steps of one. Any even modulus from
392 through 784 can also be achieved by setting the
“
double
”
bit which doubles the feedback divider modulus. The feed-
Output Description
The PCLK output is a high-current CMOS type drive
whose frequency is controlled by a programmable divider
that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12,
16 or 20. It may also be suppressed under register control
via Bit 46.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1574BEB | GT 5C 5#12 SKT RECP WALL RM |
| ICS1574BM | GT 10C 10#16 PIN RECP WALL RM |
| ICS1660 | GT 13C 13#16 PIN RECP WALL RM |
| ICS1660M | GT 13C 13#16 SKT RECP WALL RM |
| ICS1660N | GT 17C 17#16 SKT RECP WALL RM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1574BEB | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Laser Engine Pixel Clock Generator |
| ICS1574BM | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1574BMLF | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS1574BMLFT | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS1574BMT | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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