參數(shù)資料
型號(hào): ICS181M-51LF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/7頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN LOW EMI 8-SOIC
產(chǎn)品培訓(xùn)模塊: Spread Spectrum
標(biāo)準(zhǔn)包裝: 97
類型: 擴(kuò)展頻譜時(shí)鐘發(fā)生器
PLL:
輸入: 時(shí)鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 75MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
其它名稱: 181M-51LF
800-1012
800-1012-5
800-1012-ND
ICS181-51
LOW EMI CLOCK GENERATOR
SSCG
IDT / ICS LOW EMI CLOCK GENERATOR
3
ICS181-51
REV C 051310
External Components
The ICS181-51 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
value of these capacitors is given by the following
equation:
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS181-51. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS181-51. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
° C
Storage Temperature
-65 to +150
° C
Junction Temperature
125
° C
Soldering Temperature
260
° C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
° C
Power Supply Voltage (measured in respect to GND)
+3.135
+5.5
V
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