- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360744 > ICS1887M FDDI / Fast Ethernet PHYceiverTM PDF資料下載
參數(shù)資料
| 型號： | ICS1887M |
| 英文描述： | FDDI / Fast Ethernet PHYceiverTM |
| 中文描述： | FDDI的/快速以太網(wǎng)PHYceiverTM |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 536K |
| 代理商： | ICS1887M |
6
ICS1887
This circuit provides the PECL to CMOS conversion for less
than $0.80 in single unit quantities. Note that the LM393 has
two amplifiers, so the unused one is tied inactive.
A running production change will be made to the
ICS1887
to
change the CD input to PECL. Therefore, boards should be
laid out with a direct normal PECL termination connection
stuffing option. This allows either version of the part to be
used by stuffing one of two sets of external components. A
version of this circuit is shown in the diagram on the previous
page.
With
ICS1887
devices that have a TTL-compatible CD input,
the “Differential PECL to CMOS Conversion Circuit” com-
ponents need to be placed on the PCB and the “Normal PECL
Transceiver Termination” resistors (82
and 130
) as well as
the option select jumper should NOT be placed.
When the final
ICS1887
device with the PECL CD input is
used, none of the components in the “Differential PECL to
CMOS Conversion Circuit” or the “Unused amp connection”
circuits should be used. Only the four termination resistors
(87
and 130
) and the option select jumper are needed.
Note that these resistors should be located near the ends of the
transmission lines.
Clocking
Parallel data that is to be serialized for transmission must be
presented to the data transmitter device with a certain amount
of setup and hold time to a given clock.
The PDT chip expects data to setup relative to the 25 MHz
Local Symbol Clock (LSCLK). This clock is an input to the
device.
The
ICS1887
expects data to be setup relative to the 25 MHz
Reference In Clock (REF_IN). This clock is an input to the
ICS1887
device. Note that the REF_IN pin of the
ICS1887
is
a CMOS input with a switching point of 50% of VDD. If this
pin is driven by a TTL output, a pull-up resistor to VDD must
be used. The
ICS1887
device also provides a Transmit Clock
(TXC) output, which is a 50% duty cycle (nominal) copy of
the REF_IN input. The
ICS1887
is designed to provide a very
low skew between the REF_IN and the TCLK.
Loopback
The AMD PDR & PDT chips have an external loopback con-
nection between the two chips. The
ICS1887
also has a
loopback function, but it is totally internal to the device.
Optical Transmitter Off Control
The PDT chip has an input (FOTOFF) which can force an
optical transceiver to be off. The
ICS1887
performs the same
behavior with the TXOFF
~
pin.
Test Mode
Both the AMD PDR & PDT have a test mode that allows auto-
mated testers to test internal logic without the PLL clock
multiplier. The
ICS1887
does not have a similar test mode.
Transmit Current Selection
The
ICS1887
allows the PECL transmit current level to be set
externally. An 887
resistor to the VDD supply is recom-
mended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1889 | 100Base-FX Integrated PHYceiverTM |
| ICS1892 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1888 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| ICS1889 | 制造商:ICS 制造商全稱:ICS 功能描述:100Base-FX Integrated PHYceiverTM |
| ICS1890 | 制造商:ICS 制造商全稱:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICS1890Y | 制造商:ICS 功能描述: 制造商:ICS 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:ICS 功能描述:1890Y-4 制造商:Integrated Device Technology Inc 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| ICS1890Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。